XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

Ariana Musello; Esteban Garzon; Marco Lanuzza; Luis Miguel Procel; Ramiro Taco

doi:10.1109/TCSII.2023.3241163

XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

Ariana Musello, Esteban Garzon, Marco Lanuzza, Luis Miguel Procel, Ramiro Taco

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

Original language	English
Pages (from-to)	1259-1263
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	70
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2023.3241163
State	Published - 1 Mar 2023
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

BNN
CNN
Computing-in-memory
DMTJ
MAC
STT-MRAM
XNOR-bitcount
bit-quad
spin-transfer torque

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TCSII.2023.3241163

Cite this

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title = "XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs",

abstract = "This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.",

keywords = "BNN, CNN, Computing-in-memory, DMTJ, MAC, STT-MRAM, XNOR-bitcount, bit-quad, spin-transfer torque",

author = "Ariana Musello and Esteban Garzon and Marco Lanuzza and Procel, {Luis Miguel} and Ramiro Taco",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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doi = "10.1109/TCSII.2023.3241163",

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AU - Musello, Ariana

AU - Garzon, Esteban

AU - Lanuzza, Marco

AU - Procel, Luis Miguel

AU - Taco, Ramiro

PY - 2023/3/1

Y1 - 2023/3/1

N2 - This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

AB - This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (-50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

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KW - CNN

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XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

Abstract

Bibliographical note

Keywords

UN SDGs

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