Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process

Original language	American English
Title of host publication	IEEE COMCAS
State	Published - 2008

Bibliographical note

Place of conference:Israel

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Shor, J. (2008). Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process. In IEEE COMCAS

Shor, J. / Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process. IEEE COMCAS. 2008.

@inproceedings{174b386b43024a66a33db5bbd602323b,

title = "Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process",

author = "J. Shor",

note = "Place of conference:Israel",

year = "2008",

language = "American English",

booktitle = "IEEE COMCAS",

}

Shor, J 2008, Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process. in IEEE COMCAS.

Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process. / Shor, J.
IEEE COMCAS. 2008.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process

AU - Shor, J.

N1 - Place of conference:Israel

PY - 2008

Y1 - 2008

M3 - Conference contribution

BT - IEEE COMCAS

ER -

Shor J. Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process. In IEEE COMCAS. 2008