Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories

Esteban Garzon; Ramiro Taco; Luis Miguel Procel; Lionel Trojman; Marco Lanuzza

doi:10.1109/LASCAS53948.2022.9789054

Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories

Esteban Garzon
, Ramiro Taco
, Luis Miguel Procel
, Lionel Trojman
, Marco Lanuzza

University of Calabria
Universidad San Francisco de Quito
Institut Supérieur d'Électronique de Paris (ISEP)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This work presents energy advantages allowed by the technology and voltage scaling of spin-transfer torque mag-netic random access memories (STT-MRAMs) based on perpen-dicular double-barrier magnetic tunnel junction (DMTJ), with two reference layers. DMTJ is benchmarked against the single-barrier MTJ (SMTJ) -based alternative, and a comprehensive evaluation is carried out through a cross-layer simulation frame-work, considering state-of-the-art Verilog-A based SMTJ and DMTJ compact models, along with a 0.8V FinFET technology. Simulation results show that, thanks to the lower voltage op-erating point, DMTJ-based STT-MRAM allows energy savings for write/read operations of about 38%/45%, as compared to its SMTJ-based counterpart. Moreover, scaling from the 28 nm down to the 20 nm node, the DMTJ-based memory cell improves write/read energy of about 29%/33% at the expense of longer access times.

Original language	English
Title of host publication	2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665420082
DOIs	https://doi.org/10.1109/LASCAS53948.2022.9789054
State	Published - 2022
Externally published	Yes
Event	13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022 - Santiago, Chile Duration: 1 Mar 2022 → 4 Mar 2022

Publication series

Name	2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022

Conference

Conference	13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022
Country/Territory	Chile
City	Santiago
Period	1/03/22 → 4/03/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

Double-barrier magnetic tunnel junction (DMTJ)
FinFET
STT-MRAM
embedded memory
energy-efficient
low-voltage

Access to Document

10.1109/LASCAS53948.2022.9789054

Cite this

Garzon, E., Taco, R., Procel, L. M., Trojman, L., & Lanuzza, M. (2022). Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. In 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022 (2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS53948.2022.9789054

Garzon, Esteban ; Taco, Ramiro ; Procel, Luis Miguel et al. / Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022).

@inproceedings{28505395e1754cd79936141b8f7ec0ad,

title = "Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories",

abstract = "This work presents energy advantages allowed by the technology and voltage scaling of spin-transfer torque mag-netic random access memories (STT-MRAMs) based on perpen-dicular double-barrier magnetic tunnel junction (DMTJ), with two reference layers. DMTJ is benchmarked against the single-barrier MTJ (SMTJ) -based alternative, and a comprehensive evaluation is carried out through a cross-layer simulation frame-work, considering state-of-the-art Verilog-A based SMTJ and DMTJ compact models, along with a 0.8V FinFET technology. Simulation results show that, thanks to the lower voltage op-erating point, DMTJ-based STT-MRAM allows energy savings for write/read operations of about 38\%/45\%, as compared to its SMTJ-based counterpart. Moreover, scaling from the 28 nm down to the 20 nm node, the DMTJ-based memory cell improves write/read energy of about 29\%/33\% at the expense of longer access times.",

keywords = "Double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, embedded memory, energy-efficient, low-voltage",

author = "Esteban Garzon and Ramiro Taco and Procel, \{Luis Miguel\} and Lionel Trojman and Marco Lanuzza",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022 ; Conference date: 01-03-2022 Through 04-03-2022",

year = "2022",

doi = "10.1109/LASCAS53948.2022.9789054",

language = "אנגלית",

series = "2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022",

address = "ארצות הברית",

}

Garzon, E, Taco, R, Procel, LM, Trojman, L & Lanuzza, M 2022, Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. in 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022. 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022, Institute of Electrical and Electronics Engineers Inc., 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022, Santiago, Chile, 1/03/22. https://doi.org/10.1109/LASCAS53948.2022.9789054

Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. / Garzon, Esteban; Taco, Ramiro; Procel, Luis Miguel et al.
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories

AU - Garzon, Esteban

AU - Taco, Ramiro

AU - Procel, Luis Miguel

AU - Trojman, Lionel

AU - Lanuzza, Marco

PY - 2022

Y1 - 2022

N2 - This work presents energy advantages allowed by the technology and voltage scaling of spin-transfer torque mag-netic random access memories (STT-MRAMs) based on perpen-dicular double-barrier magnetic tunnel junction (DMTJ), with two reference layers. DMTJ is benchmarked against the single-barrier MTJ (SMTJ) -based alternative, and a comprehensive evaluation is carried out through a cross-layer simulation frame-work, considering state-of-the-art Verilog-A based SMTJ and DMTJ compact models, along with a 0.8V FinFET technology. Simulation results show that, thanks to the lower voltage op-erating point, DMTJ-based STT-MRAM allows energy savings for write/read operations of about 38%/45%, as compared to its SMTJ-based counterpart. Moreover, scaling from the 28 nm down to the 20 nm node, the DMTJ-based memory cell improves write/read energy of about 29%/33% at the expense of longer access times.

AB - This work presents energy advantages allowed by the technology and voltage scaling of spin-transfer torque mag-netic random access memories (STT-MRAMs) based on perpen-dicular double-barrier magnetic tunnel junction (DMTJ), with two reference layers. DMTJ is benchmarked against the single-barrier MTJ (SMTJ) -based alternative, and a comprehensive evaluation is carried out through a cross-layer simulation frame-work, considering state-of-the-art Verilog-A based SMTJ and DMTJ compact models, along with a 0.8V FinFET technology. Simulation results show that, thanks to the lower voltage op-erating point, DMTJ-based STT-MRAM allows energy savings for write/read operations of about 38%/45%, as compared to its SMTJ-based counterpart. Moreover, scaling from the 28 nm down to the 20 nm node, the DMTJ-based memory cell improves write/read energy of about 29%/33% at the expense of longer access times.

KW - Double-barrier magnetic tunnel junction (DMTJ)

KW - FinFET

KW - STT-MRAM

KW - embedded memory

KW - energy-efficient

KW - low-voltage

UR - https://www.scopus.com/pages/publications/85133202392

U2 - 10.1109/LASCAS53948.2022.9789054

DO - 10.1109/LASCAS53948.2022.9789054

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:85133202392

T3 - 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022

BT - 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022

Y2 - 1 March 2022 through 4 March 2022

ER -

Garzon E, Taco R, Procel LM, Trojman L, Lanuzza M. Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. In 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022. Institute of Electrical and Electronics Engineers Inc. 2022. (2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022). doi: 10.1109/LASCAS53948.2022.9789054

Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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