Verifying hardware in its software context and vice-versa

R. P. Kurshan (Inventor), V. Levin (Inventor), M. Minea (Inventor), D. Peled (Inventor), H. Yenigun (Inventor)

Research output: Patent


A method and apparatus that employs static partial order reduction and symbolic verification allow the design of a system that includes both hardware and software to be verified. The system is specified in a hardware-centric language and a software-centric language, as appropriate, and properties are verified one at a time. Each property is identified whether it is hardware-centric or software-centric. A hardware-centric property that contains little software is does not employ the static partial order reduction. Software-centric properties, and hardware-centric properties that have substantial amounts of software do employ the static partial order reduction. Following partial order reduction, the software-centric language specifications are converted to synchronous form and combined with the hardware-centric specifications. The combined specification is applied to a symbolic verification tool, such as COSPAN, and the results are displayed.
Original languageAmerican English
Patent numberUS6209120 B1
StatePublished - 2001


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