TY - GEN
T1 - Use of gray decoding for implementation of symmetric functions
AU - Keren, Osnat
AU - Levin, Ilya
AU - Stankovic, Radomir S.
PY - 2007
Y1 - 2007
N2 - This paper discusses reduction of the number of product terms in representation of totally symmetric Boolean functions by Sum of Products (SOP) and Fixed Polarity Reed-Muller (FPRM) expansions. The suggested method reduces the number of product terms, correspondingly, the implementation cost of symmetric functions based on these expressions by exploiting Gray decoding of input variables. Although this decoding is a particular example of all possible linear transformation of Boolean variables, it is efficient in the case of symmetric functions since it provides a significant simplification of SOPs and FPRMs. Mathematical analysis as well as experimental results demonstrate the efficiency of the proposed method.
AB - This paper discusses reduction of the number of product terms in representation of totally symmetric Boolean functions by Sum of Products (SOP) and Fixed Polarity Reed-Muller (FPRM) expansions. The suggested method reduces the number of product terms, correspondingly, the implementation cost of symmetric functions based on these expressions by exploiting Gray decoding of input variables. Although this decoding is a particular example of all possible linear transformation of Boolean variables, it is efficient in the case of symmetric functions since it provides a significant simplification of SOPs and FPRMs. Mathematical analysis as well as experimental results demonstrate the efficiency of the proposed method.
KW - Autocorrelation
KW - Gray code
KW - Linear transformation
KW - Symmetric function
UR - http://www.scopus.com/inward/record.url?scp=50149103458&partnerID=8YFLogxK
U2 - 10.1109/VLSISOC.2007.4402467
DO - 10.1109/VLSISOC.2007.4402467
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AN - SCOPUS:50149103458
SN - 9781424417100
T3 - 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
SP - 25
EP - 30
BT - 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
T2 - 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
Y2 - 15 October 2007 through 17 October 2007
ER -