Ultra low voltage synthesizable memories: A trade-off discussion in 65 nm CMOS

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch architecture designs, and process options. Furthermore, deployment of multiple threshold voltages (V_th) options in a single standard-cell/bitcell enables additional architectural choices. Silicon measurements from five memory designs, optimized at the transistor level in conjunction with gate-level optimizations, are considered to demonstrate the different trade-off corners. Measurements show that substituting the storage element in an SCM with a D-latch using transistor stacking and channel length stretching results in lowest leakage power. Alternatively, a pass-transistor based latch as storage element reduces the area footprint at a cost of reduced access speed, which can be compensated by using a lower- V_th pass-transistor. However, relatively high speed (tens of MHz) in the near- to subthreshold (V_th) region is achievable if general purpose transistors are used instead of low power transistors. A discussion is included to illustrate when to implement ULV memories using SCMs and when to choose sub- V_th SRAMs. The discussion shows that the border is between 4-6 kb, depending on the number of words and the wordlength configuration.