TY - PAT
T1 - Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation
AU - Teman, A.
AU - Pergament, L
AU - Cohen, O
PY - 2013
Y1 - 2013
N2 - An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The supply node is coupled via a gating device to a supply voltage and ground node is connected to ground. In addition, storage node Q is fed back via feedback loop into a control node of the gating device. In operation, writing into the memory cell may be carried out in a similar manner to dual port SRAM cells, utilizing one or two write circuitries and for writing into storage node Q and storage node QB respectively. Differently from standard SRAM cells, the feedback loop, by controlling the gating device is configured to weaken the write contention.
AB - An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The supply node is coupled via a gating device to a supply voltage and ground node is connected to ground. In addition, storage node Q is fed back via feedback loop into a control node of the gating device. In operation, writing into the memory cell may be carried out in a similar manner to dual port SRAM cells, utilizing one or two write circuitries and for writing into storage node Q and storage node QB respectively. Differently from standard SRAM cells, the feedback loop, by controlling the gating device is configured to weaken the write contention.
UR - https://scholar.google.co.il/scholar?q=Ultra+low+power+sram+cell+circuit+with+a+supply+feedback+loop+for+near+and+sub+threshold+operation&btnG=&hl=en&as_sdt=0%2C5
M3 - Patent
M1 - 8,531,873
PB - Washington, DC: U.S. Patent and Trademark Office
ER -