Ultra low-power off based shift registers design for CMOS image sensors applications

Various implementations of D-Flip-Flops (DFF) for shift register designs in CMOS image sensors are proposed. Driven by requirements of low-area and low-power dissipation, the presented FFs allow implementation of power-efficient shift registers, used for signal readout control and windows of interest definition in CMOS image sensors and are optimized for operation at low frequencies. Power dissipation of the presented DFFs is significantly reduced by leakage control using the stack effect. A variety of DFFs and a shift-register, using the stacking effect approach, have been implemented in 0.1 μm standard CMOS technology to compare the proposed DFFs and shift-register structures with existing alternatives, showing an up-to 63% reduction in power dissipation of a shift-register at 30Hz frequency. Operation of the proposed circuits is discussed and simulation results are reported.