Two-port low-power gain-cell storage array: Voltage scaling and retention time

Rashid Iqbal, Pascal Meinerzhagen, Andreas Burg

Research output: Contribution to conferencePaperpeer-review

8 Scopus citations

Abstract

The impact of supply voltage scaling on the retention time of a 2-transistor (2T) gain-cell (GC) storage array is investigated, in order to enable low-power/low-voltage data storage. The retention time can be increased when scaling down the supply voltage for a given access statistics and a given write bit-line (WBL) control scheme. Moreover, for a given supply voltage, the retention time can be further increased by controlling the WBL to a voltage level between the supply rails during idle and read states. These two concepts are proved by means of Spectre simulation of a GC-storage array implemented in 180-nm CMOS technology. The proposed 2-kb storage macro is operated at only 40% of the nominal supply voltage and leverages the GCs to enable two-port operation with a negligible area-increase compared to a single-port implementation.

Original languageEnglish
Pages2469-2472
Number of pages4
DOIs
StatePublished - 2012
Externally publishedYes
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

Fingerprint

Dive into the research topics of 'Two-port low-power gain-cell storage array: Voltage scaling and retention time'. Together they form a unique fingerprint.

Cite this