Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits

Alexander Kushnerov, Moti Medina, Alexandre Yakovlev

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazard-free MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.

Original languageEnglish
Title of host publicationProceedings - 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021
PublisherIEEE Computer Society
Pages17-24
Number of pages8
ISBN (Electronic)9781728141329
DOIs
StatePublished - 2021
Event27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021 - Virtual, Online, China
Duration: 7 Sep 202110 Sep 2021

Publication series

NameProceedings - International Symposium on Asynchronous Circuits and Systems
Volume2021-September
ISSN (Print)2643-1394
ISSN (Electronic)2643-1483

Conference

Conference27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021
Country/TerritoryChina
CityVirtual, Online
Period7/09/2110/09/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE

Funding

We would like to thank Boris S. Tsirlin for discussing the very idea of using multiplexers in semimodular circuits and for his patents. We are also grateful to Danil Sokolov, who realized the binate consensus verification in Workcraft. This research was partially supported by ISF, grant 867/19 and by EPSRC, grant EP/N023641/1 "STRATA". Wewould like to thankBoris S. Tsirlinfordiscussingthevery idea of using multiplexers in semimodular circuits and for his patents. We are also gratefulto Danil Sokolov, who realized the binate consensus verification in Workcraft. This research was partially supported by ISF, grant 867/19 and by EPSRC, grant EP/N023641/1 "STRATA".

FundersFunder number
Boris S. Tsirlin
Engineering and Physical Sciences Research CouncilEP/N023641/1
Israel Science Foundation867/19

    Keywords

    • Binate function
    • C-element
    • Consensus cube
    • Hazard
    • Lookup table
    • Multiplexer
    • QDI circuit

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