TY - GEN
T1 - Towards generic low-power area-efficient standard cell based memory architectures
AU - Meinerzhagen, P.
AU - Roth, C.
AU - Burg, A.
PY - 2010
Y1 - 2010
N2 - Digital IC designers often use SRAM macrocells to implement on-chip memory functionality. In this paper we argue that in several situations, standard cell based memories (SCMs) can have advantages over SRAM macrocells. Various ways to implement SCMs are presented and compared to each other for different CMOS technologies and standard cell libraries and to corresponding macrocells, aiming for finding the most adequate memory option for each application. The benefits and drawbacks of SCMs compared to macrocells are illustrated with the example of a low-power low-density parity check (LDPC) decoder.
AB - Digital IC designers often use SRAM macrocells to implement on-chip memory functionality. In this paper we argue that in several situations, standard cell based memories (SCMs) can have advantages over SRAM macrocells. Various ways to implement SCMs are presented and compared to each other for different CMOS technologies and standard cell libraries and to corresponding macrocells, aiming for finding the most adequate memory option for each application. The benefits and drawbacks of SCMs compared to macrocells are illustrated with the example of a low-power low-density parity check (LDPC) decoder.
UR - http://www.scopus.com/inward/record.url?scp=77956600661&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2010.5548579
DO - 10.1109/MWSCAS.2010.5548579
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AN - SCOPUS:77956600661
SN - 9781424477715
T3 - Midwest Symposium on Circuits and Systems
SP - 129
EP - 132
BT - 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010
T2 - 53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010
Y2 - 1 August 2010 through 4 August 2010
ER -