Many SMT solvers implement efficient SAT-based procedures for solving fixed-size bit-vector formulas. These approaches, however, cannot be used directly to reason about bit-vectors of symbolic bit-width. To address this shortcoming, we propose a translation from bit-vector formulas with parametric bit-width to formulas in a logic supported by SMT solvers that includes non-linear integer arithmetic, uninterpreted functions, and universal quantification. While this logic is undecidable, this approach can still solve many formulas by capitalizing on advances in SMT solving for non-linear arithmetic and universally quantified formulas. We provide several case studies in which we have applied this approach with promising results, including the bit-width independent verification of invertibility conditions, compiler optimizations, and bit-vector rewrites.
|Title of host publication||Automated Deduction – CADE 2019- 27th International Conference on Automated Deduction, Proceedings|
|Number of pages||19|
|State||Published - 2019|
|Event||27th International Conference on Automated Deduction, CADE 2019 - Natal, Brazil|
Duration: 27 Aug 2019 → 30 Aug 2019
|Name||Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|
|Conference||27th International Conference on Automated Deduction, CADE 2019|
|Period||27/08/19 → 30/08/19|
Bibliographical noteFunding Information:
This work was supported in part by DARPA (awards N66001-18-C-4012 and FA8650-18-2-7861), ONR (award N68335-17-C-0558), NSF (award 1656926), and the Stanford Center for Blockchain Research.
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