Towards a DML Optimized Synthesis

Itamar Levi; Alexander Fish

doi:10.1007/978-3-030-40786-5_8

Towards a DML Optimized Synthesis

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

In the previous chapter we discussed ways how to characterize DML cells into several libraries and use these with standard EDA tools. In this chapter we outline an optimized synthesis procedure for DML design. In a nutshell, this methodology involves changing certain...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Publisher	Springer
Pages	143-155
Number of pages	13
DOIs	https://doi.org/10.1007/978-3-030-40786-5_8
State	Published - 16 Dec 2020

Keywords

Standard cell library
Standard flow
Characterization
Electronic design automation (EDA)
Automation
ASIC
RTL-synthesis
Static timing analysis (STA)
Pseudo-static
Liberty
Post-synthesis
Gate level (GTL)
Hardware description language (HDL)
Constraints
Correct precharge (CPC)
Footed gates (FG)
Single transition requirement (STR)
Glitching
Perl
ISCAS benchmarks
DML synthesis
DML

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10.1007/978-3-030-40786-5_8

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Towards a DML Optimized Synthesis

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Keywords

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