Towards a DML Optimized Synthesis

Research output: Chapter in Book/Report/Conference proceedingChapter


In the previous chapter we discussed ways how to characterize DML cells into several libraries and use these with standard EDA tools. In this chapter we outline an optimized synthesis procedure for DML design. In a nutshell, this methodology involves changing certain...
Original languageEnglish
Title of host publicationDual Mode Logic
Place of PublicationCham, Switzerland
Number of pages13
StatePublished - 16 Dec 2020


  • Standard cell library
  • Standard flow
  • Characterization
  • Electronic design automation (EDA)
  • Automation
  • ASIC
  • RTL-synthesis
  • Static timing analysis (STA)
  • Pseudo-static
  • Liberty
  • Post-synthesis
  • Gate level (GTL)
  • Hardware description language (HDL)
  • Constraints
  • Correct precharge (CPC)
  • Footed gates (FG)
  • Single transition requirement (STR)
  • Glitching
  • Perl
  • ISCAS benchmarks
  • DML synthesis
  • DML


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