Towards a DML Library Characterization and Design with Standard Flow

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

After discussing the DML foundations and presenting several conceptual use cases of DML, we now introduce the reader to ways to scale up the utilization space of DML. Specifically, this chapter presents an approach to a DML cell-library characterization and describes...
Original languageEnglish
Title of host publicationDual Mode Logic
Place of PublicationCham, Switzerland
PublisherSpringer
Pages115-142
Number of pages28
DOIs
StatePublished - 16 Dec 2020

Keywords

  • Standard cell library
  • Standard flow
  • Characterization
  • Electronic design automation (EDA)
  • Automation
  • ASIC
  • RTL-synthesis
  • Static timing analysis (STA)
  • Non-unate
  • Monotonicity
  • Cascading
  • Duplication
  • Pseudo-static
  • Liberty
  • Connection class
  • Cadence
  • Synopsis
  • Mapping
  • Violation
  • Crossed cells
  • Post-synthesis
  • Footless
  • Dummy cells
  • Semi-footed cells
  • Area expansion
  • Gate count
  • Speedup
  • Slowdown
  • DML synthesis
  • DML

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