Abstract
SRAM stability analysis has become a primary issue in the design of memories. While the classic definition of static noise margin based on butterfly curves was once enough to determine SRAM stability and properly size the transistors of a 6T bitcell, the recent trends of technology and supply voltage scaling have caused SRAM yield to decrease significantly. As a result, more complex methodologies for stability analysis have been suggested in the form of dynamic noise margins. In this paper, a brief review of static and dynamic analysis methods is given, along with the advantages and disadvantages of each approach. Ultimately, a combination of these approaches should lead to the development of a complete toolkit for stability analysis in the deep-nanoscale era.
Original language | English |
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Title of host publication | 2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781479959877 |
DOIs | |
State | Published - 2014 |
Event | 2014 28th IEEE Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014 - Eilat, Israel Duration: 3 Dec 2014 → 5 Dec 2014 |
Publication series
Name | 2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014 |
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Conference
Conference | 2014 28th IEEE Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014 |
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Country/Territory | Israel |
City | Eilat |
Period | 3/12/14 → 5/12/14 |
Bibliographical note
Publisher Copyright:© Copyright 2015 IEEE All rights reserved.
Keywords
- Dynamic noise margin
- SRAM
- Separatrix
- Stability analysis
- Static noise margin