Abstract
We present an error-correcting architecture for cryptographic circuits that are exposed to maliciously injected faults. The architecture is based on a new class of error-detecting and correcting codes, which combine high rate, large distance, and robustness; that is, they can detect all error patterns injected by a skillful and strategic attacker and automatically correct simpler errors. Correction of errors is superior to detection since it avoids service disruptions and system-level recovery actions. We investigate the architectures using both mathematical analysis and physical fault injection on an field programmable gate array (FPGA) platform, and point out critical divergences between these methods and the need to employ both of them.
| Original language | English |
|---|---|
| Article number | 8673322 |
| Pages (from-to) | 115-118 |
| Number of pages | 4 |
| Journal | IEEE Embedded Systems Letters |
| Volume | 11 |
| Issue number | 4 |
| DOIs | |
| State | Published - Dec 2019 |
Bibliographical note
Publisher Copyright:© 2009-2012 IEEE.
Funding
Manuscript received July 9, 2018; revised November 18, 2018; accepted March 8, 2019. Date of publication March 24, 2019; date of current version November 21, 2019. This work was supported in part by Deutsche Forschungsgemeinschaft under Grant PO 1220/7-2, and in part by the Israel Science Foundation under Grant 932/16. This manuscript was recommended for publication by A. Canedo, M. Al Faruque, and F. Regazzoni. (Corresponding author: Ilia Polian.) M. Gay and I. Polian are with the Institute of Computer Engineering and Computer Architecture, University of Stuttgart, 70569 Stuttgart, Germany (e-mail: [email protected]).
| Funders | Funder number |
|---|---|
| Deutsche Forschungsgemeinschaft | PO 1220/7-2 |
| Israel Science Foundation | 932/16 |
Keywords
- Error-detecting and correcting codes
- fault-injection attacks
- safety- and security-critical systems