Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing

Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


Reduction of interconnect delay and interconnect power has become a primary design challenge in recent CMOS technology generations. Spacing between wires can be modified so that line-to-line capacitances will be optimized for minimal power under timing constraints. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing that minimizes the total dynamic power dissipation caused by an interconnect, while maximum delay constraints are satisfied. A multidimensional visibility graph is used to represent the problem, and a layout partitioning technique is applied to solve the problem efficiently. The algorithm was evaluated on an industrial microprocessor designed using the 32 nm technology, and it achieved a 5-12% reduction in interconnect switching power.

Original languageEnglish
Pages (from-to)116-128
Number of pages13
JournalIntegration, the VLSI Journal
Issue number1
StatePublished - 2015

Bibliographical note

Publisher Copyright:
© 2014 Elsevier B.V. All rights reserved.


  • Constrained optimization
  • Interconnect sizing and spacing
  • Power-delay optimization


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