Tight-ES-TRNG: Improved Construction and Robustness Analysis

Recently in CHES-2018 Yang et al. demonstrated a very low cost and high performance true random number generator (TRNG) dubbed ES-TRNG. The main novelty of this class of TRNGs is in the methodology of extracting entropy from the accumulated phase jitter, i.e., by using a mechanism of repeatedly sample high-speed clock-edges with high resolution. In this manuscript, we demonstrate how it is possible to increase the number of edges in a cycle (with a very low cost) such that edges accommodate more and more from the full distribution of the phase jitter (this is where the “tightness” is coming from). By utilizing this mechanism we are able to reduce the number of required “repeated samples” (as compared to the ES-TRNG) and to substantially increase the achievable entropy level. We show how it is possible to fine-grain balance the implemented Ring-Oscillators (ROs) periods on FPGAs by using specialized constraints, such as controlling LUTs inputs and distance between elements. We evaluate the validity of our design with the NIST SP800-90B entropy evaluation suite and support the results with a stochastic model which augments the model of Yang et al. to take into account our new design characteristics. The proposed design is able to achieve 5.6 Mbps with an estimated (worst-case) min-entropy level of 0.88 bits—without post-processing (on the raw samples). On the same platform and under the same conditions (i.e. without post-processing), the ES-TRNG was able to maximally produce 1.6 Mbps with min-entropy of 0.5. The manuscript is concluded with a cautionary note and robustness analysis of this class of TRNGs. We demonstrate how dangerous is the affect of parameters such as the external temperature, slow drifts in the power supply voltage, and transient noise (due to logic activity). In essence, we show how small drifts in these parameters concretely reduce both efficiency and the estimated min-entropy levels of the TRNG.