The optimal fan-out of clock network for power minimization by adaptive gating

Shmuel Wimer, Israel Koren

Research output: Contribution to journalArticlepeer-review

34 Scopus citations


Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. In this paper we develop a probabilistic model of the clock gating network that allows us to quantify the expected power savings and the implied overhead. Expressions for the power savings in a gated clock tree are presented and the optimal gater fan-out is derived, based on flip-flops toggling probabilities and process technology parameters. The resulting clock gating methodology achieves 10% savings of the total clock tree switching power. The timing implications of the proposed gating scheme are discussed. The grouping of FFs for a joint clocked gating is also discussed. The analysis and the results match the experimental data obtained for a 3-D graphics processor and a 16-bit microcontroller, both designed at 65-nanometer technology.

Original languageEnglish
Article number5993481
Pages (from-to)1772-1780
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
StatePublished - 2012

Bibliographical note

Funding Information:
Manuscript received April 25, 2011; revised July 08, 2011; accepted July 19, 2011. Date of publication August 22, 2011; date of current version July 19, 2012. This work was supported in part by MAGNET Program of Israel Ministry of Industry. S. Wimer is with the School of Engineering, Bar-Ilan University, Ramat-Gan 52900, Israel (e-mail: I. Koren is with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003 USA (e-mail: koren@ecs.umass. edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier 10.1109/TVLSI.2011.2162861


  • Clock gating
  • clock networks
  • clock tree
  • dynamic power minimization
  • optimal fan-out


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