The optimal fan-out of clock network for power minimization by adaptive gating

Shmuel Wimer; Israel Koren

doi:10.1109/tvlsi.2011.2162861

The optimal fan-out of clock network for power minimization by adaptive gating

Shmuel Wimer, Israel Koren

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

University of Massachusetts

Research output: Contribution to journal › Article › peer-review

36 Scopus citations

Abstract

Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. In this paper we develop a probabilistic model of the clock gating network that allows us to quantify the expected power savings and the implied overhead. Expressions for the power savings in a gated clock tree are presented and the optimal gater fan-out is derived, based on flip-flops toggling probabilities and process technology parameters. The resulting clock gating methodology achieves 10% savings of the total clock tree switching power. The timing implications of the proposed gating scheme are discussed. The grouping of FFs for a joint clocked gating is also discussed. The analysis and the results match the experimental data obtained for a 3-D graphics processor and a 16-bit microcontroller, both designed at 65-nanometer technology.

Original language	English
Article number	5993481
Pages (from-to)	1772-1780
Number of pages	9
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	20
Issue number	10
DOIs	https://doi.org/10.1109/tvlsi.2011.2162861
State	Published - 2012

Bibliographical note

Funding Information:
Manuscript received April 25, 2011; revised July 08, 2011; accepted July 19, 2011. Date of publication August 22, 2011; date of current version July 19, 2012. This work was supported in part by MAGNET Program of Israel Ministry of Industry. S. Wimer is with the School of Engineering, Bar-Ilan University, Ramat-Gan 52900, Israel (e-mail: [email protected]). I. Koren is with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003 USA (e-mail: [email protected]. edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2011.2162861

Funding

Manuscript received April 25, 2011; revised July 08, 2011; accepted July 19, 2011. Date of publication August 22, 2011; date of current version July 19, 2012. This work was supported in part by MAGNET Program of Israel Ministry of Industry. S. Wimer is with the School of Engineering, Bar-Ilan University, Ramat-Gan 52900, Israel (e-mail: [email protected]). I. Koren is with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003 USA (e-mail: [email protected]. edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2011.2162861

Funders	Funder number
MAGNET Program of Israel Ministry of Industry

Keywords

Clock gating
clock networks
clock tree
dynamic power minimization
optimal fan-out

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10.1109/tvlsi.2011.2162861

Cite this

@article{354365d8a0e241619849140f16a144c5,

title = "The optimal fan-out of clock network for power minimization by adaptive gating",

abstract = "Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. In this paper we develop a probabilistic model of the clock gating network that allows us to quantify the expected power savings and the implied overhead. Expressions for the power savings in a gated clock tree are presented and the optimal gater fan-out is derived, based on flip-flops toggling probabilities and process technology parameters. The resulting clock gating methodology achieves 10% savings of the total clock tree switching power. The timing implications of the proposed gating scheme are discussed. The grouping of FFs for a joint clocked gating is also discussed. The analysis and the results match the experimental data obtained for a 3-D graphics processor and a 16-bit microcontroller, both designed at 65-nanometer technology.",

keywords = "Clock gating, clock networks, clock tree, dynamic power minimization, optimal fan-out",

author = "Shmuel Wimer and Israel Koren",

note = "Funding Information: Manuscript received April 25, 2011; revised July 08, 2011; accepted July 19, 2011. Date of publication August 22, 2011; date of current version July 19, 2012. This work was supported in part by MAGNET Program of Israel Ministry of Industry. S. Wimer is with the School of Engineering, Bar-Ilan University, Ramat-Gan 52900, Israel (e-mail: [email protected]). I. Koren is with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003 USA (e-mail: [email protected]. edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2011.2162861",

year = "2012",

doi = "10.1109/tvlsi.2011.2162861",

language = "אנגלית",

volume = "20",

pages = "1772--1780",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - The optimal fan-out of clock network for power minimization by adaptive gating

AU - Wimer, Shmuel

AU - Koren, Israel

N1 - Funding Information: Manuscript received April 25, 2011; revised July 08, 2011; accepted July 19, 2011. Date of publication August 22, 2011; date of current version July 19, 2012. This work was supported in part by MAGNET Program of Israel Ministry of Industry. S. Wimer is with the School of Engineering, Bar-Ilan University, Ramat-Gan 52900, Israel (e-mail: [email protected]). I. Koren is with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003 USA (e-mail: [email protected]. edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2011.2162861

PY - 2012

Y1 - 2012

N2 - Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. In this paper we develop a probabilistic model of the clock gating network that allows us to quantify the expected power savings and the implied overhead. Expressions for the power savings in a gated clock tree are presented and the optimal gater fan-out is derived, based on flip-flops toggling probabilities and process technology parameters. The resulting clock gating methodology achieves 10% savings of the total clock tree switching power. The timing implications of the proposed gating scheme are discussed. The grouping of FFs for a joint clocked gating is also discussed. The analysis and the results match the experimental data obtained for a 3-D graphics processor and a 16-bit microcontroller, both designed at 65-nanometer technology.

AB - Gating of the clock signal in VLSI chips is nowadays a mainstream design methodology for reducing switching power consumption. In this paper we develop a probabilistic model of the clock gating network that allows us to quantify the expected power savings and the implied overhead. Expressions for the power savings in a gated clock tree are presented and the optimal gater fan-out is derived, based on flip-flops toggling probabilities and process technology parameters. The resulting clock gating methodology achieves 10% savings of the total clock tree switching power. The timing implications of the proposed gating scheme are discussed. The grouping of FFs for a joint clocked gating is also discussed. The analysis and the results match the experimental data obtained for a 3-D graphics processor and a 16-bit microcontroller, both designed at 65-nanometer technology.

KW - Clock gating

KW - clock networks

KW - clock tree

KW - dynamic power minimization

KW - optimal fan-out

UR - http://www.scopus.com/inward/record.url?scp=84864758697&partnerID=8YFLogxK

U2 - 10.1109/tvlsi.2011.2162861

DO - 10.1109/tvlsi.2011.2162861

M3 - ???researchoutput.researchoutputtypes.contributiontojournal.article???

AN - SCOPUS:84864758697

SN - 1063-8210

VL - 20

SP - 1772

EP - 1780

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 10

M1 - 5993481

ER -

The optimal fan-out of clock network for power minimization by adaptive gating

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Keywords

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