Testing concepts of advanced rad-hard SoC

Tuvia Liran, Ran Ginosar, Reuven Dobkin, Dov Alon

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Advanced System on Chip (SoC) devices for space applications require very high reliability and quality, while maintaining high performance. They require high integration level, high speed, and immunity to all radiation effects. Protecting against soft errors leads to an increased number of memory bits, increased gate count and die size and higher power. On top of that, the need for high quality by high test coverage requires special testability features like SCAN, and extensive memory access. The use of Iddq testing provides significant improvement of test coverage, forcing some design restrictions. It provides additional test coverage, beyond the coverage of conventional tests and without stressing the devices. The production test includes also high voltage stress (HVS) procedure that stresses some of the failure mechanisms. By comparing Iddq before and after the HVS, it is possible to detect degradation at early stage, even before the functional failure has developed, which makes it efficient screening method. The methodology for covering almost all failure mechanisms in the SRAMs is based on internal testability features and on test patterns based on MARCH-C algorithm. The key concepts employed for testing of some rad-hard space SoC devices are described in this paper.

Original languageEnglish
Title of host publicationProceedings of DASIA 2012 - DAta Systems In Aerospace
StatePublished - 2012
Externally publishedYes
EventDAta Systems In Aerospace, DASIA 2012 - Dubrovnik, Croatia
Duration: 14 May 201216 May 2012

Publication series

NameEuropean Space Agency, (Special Publication) ESA SP
Volume701 SP
ISSN (Print)0379-6566

Conference

ConferenceDAta Systems In Aerospace, DASIA 2012
Country/TerritoryCroatia
CityDubrovnik
Period14/05/1216/05/12

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