TY - GEN
T1 - TamaRISC-CS
T2 - 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012
AU - Constantin, Jeremy
AU - Dogan, Ahmed
AU - Andersson, Oskar
AU - Meinerzhagen, Pascal
AU - Rodrigues, Joachim Neves
AU - Atienza, David
AU - Burg, Andreas
PY - 2012
Y1 - 2012
N2 - Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-VT) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-VT operation. Therefore, we propose a sub-VT application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor.
AB - Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-VT) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-VT operation. Therefore, we propose a sub-VT application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor.
UR - http://www.scopus.com/inward/record.url?scp=84872183309&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2012.6379023
DO - 10.1109/VLSI-SoC.2012.6379023
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AN - SCOPUS:84872183309
SN - 9781467326568
T3 - 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012 - Proceedings
SP - 159
EP - 164
BT - 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012 - Proceedings
Y2 - 7 October 2012 through 10 October 2012
ER -