Abstract
Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-VT) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-VT operation. Therefore, we propose a sub-VT application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor.
Original language | English |
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Title of host publication | 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012 |
Publisher | IEEE Computer Society |
Pages | 159-164 |
Number of pages | 6 |
ISBN (Electronic) | 9781467326582 |
DOIs | |
State | Published - 18 Nov 2015 |
Externally published | Yes |
Event | IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012 - Santa Cruz, United States Duration: 7 Oct 2012 → 10 Oct 2012 |
Publication series
Name | IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC |
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Volume | 07-10-October-2012 |
ISSN (Print) | 2324-8432 |
ISSN (Electronic) | 2324-8440 |
Conference
Conference | IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012 |
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Country/Territory | United States |
City | Santa Cruz |
Period | 7/10/12 → 10/10/12 |
Bibliographical note
Publisher Copyright:© 2012 IEEE.