Systematic design of RSSI and logarithmic amplifiers circuits

Y. Melamed, A. Even-Chen, Solon J. Spiegel

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    8 Scopus citations

    Abstract

    This paper presents a systematic design methodology for logarithmic amplifiers and receiver signal strength indicator (RSSI) circuits. A close expression for the maximum detection error using a piece wise linear approximation of the logarithmic function was derived. The design methodology has been proposed that optimizes the power consumption and 3dB bandwidth of a single stage CMOS limiting amplifier according to the common mode voltages in order to meet the voltage gain and detection error requirements. The results for the RSSI circuit indicate 70dB dynamic range, 3dB bandwidth of 500MHz and maximum detection error of 0.6dB in the temperature range between -40°C and +70°C. The overall power consumption equals to 10.3mW in 180nm CMOS process technology.

    Original languageEnglish
    Title of host publication2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems, COMCAS 2009
    DOIs
    StatePublished - 2009
    Event2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems, COMCAS 2009 - Tel Aviv, Israel
    Duration: 9 Nov 200911 Nov 2009

    Publication series

    Name2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems, COMCAS 2009

    Conference

    Conference2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems, COMCAS 2009
    Country/TerritoryIsrael
    CityTel Aviv
    Period9/11/0911/11/09

    Keywords

    • Logarithmic amplifiers
    • Power detectors
    • RSSI
    • Signal detection

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