Synthesis of ASM-based self-checking controllers

I. Levin, V. Sinelnikov, M. Karpovsky

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations


In this paper we present a new technique for on-line checking of FPGA-based sequential devices defined by their algorithmic state machines (ASMs). The technique utilizes specific properties of ASMs for achieving the totally self-checking goal with a low hardware overhead. This technique is based on the architecture that consists of two portions: a self-checking sequential device and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an "evolution" block and an "execution" block. Comparison of code vectors transferred between these blocks provides for the totally self-checking property. The proposed technique does not require any redundant encoding of output words and uses a one-rail design, thereby drastically decreasing the required overhead. The paper presents overhead estimations and results for benchmarks for the proposed architecture.

Original languageEnglish
Title of host publicationProceedings - Euromicro Symposium on Digital Systems Design
Subtitle of host publicationArchitectures, Methods and Tools, DSD 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages7
ISBN (Electronic)0769512399, 9780769512396
StatePublished - 2001
Externally publishedYes
EventEuromicro Symposium on Digital Systems Design, DSD 2001 - Warsaw, Poland
Duration: 4 Sep 20016 Sep 2001

Publication series

NameProceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001


ConferenceEuromicro Symposium on Digital Systems Design, DSD 2001

Bibliographical note

Publisher Copyright:
© 2001 IEEE.


This research was supported by BSF under grant No. 9800154.

FundersFunder number
United States-Israel Binational Science Foundation9800154


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