In this paper we present a new technique for on-line checking of FPGA-based sequential devices defined by their algorithmic state machines (ASMs). The technique utilizes specific properties of ASMs for achieving the totally self-checking goal with a low hardware overhead. This technique is based on the architecture that consists of two portions: a self-checking sequential device and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an "evolution" block and an "execution" block. Comparison of code vectors transferred between these blocks provides for the totally self-checking property. The proposed technique does not require any redundant encoding of output words and uses a one-rail design, thereby drastically decreasing the required overhead. The paper presents overhead estimations and results for benchmarks for the proposed architecture.
|Title of host publication||Proceedings - Euromicro Symposium on Digital Systems Design|
|Subtitle of host publication||Architectures, Methods and Tools, DSD 2001|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||7|
|ISBN (Electronic)||0769512399, 9780769512396|
|State||Published - 2001|
|Event||Euromicro Symposium on Digital Systems Design, DSD 2001 - Warsaw, Poland|
Duration: 4 Sep 2001 → 6 Sep 2001
|Name||Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001|
|Conference||Euromicro Symposium on Digital Systems Design, DSD 2001|
|Period||4/09/01 → 6/09/01|
Bibliographical noteFunding Information:
This research was supported by BSF under grant No. 9800154.
© 2001 IEEE.