TY - GEN
T1 - Sub-threshold and near-threshold SRAM design
AU - Teman, Adam
AU - Fish, Alexander
PY - 2010
Y1 - 2010
N2 - Voltage scaling is one of the most effective techniques for power reduction in digital VLSI design, however various challenges arise when operating standard SRAM circuits at low voltages. These include loss of static noise margins, extreme fluctuations in device currents under process variations and limitations on the number of cells connected to a single bitline. In this paper, we describe the challenges that arise while operating standard SRAM cells at low supply voltages and review several novel bitcells that have been presented in recent years to deal with these challenges.
AB - Voltage scaling is one of the most effective techniques for power reduction in digital VLSI design, however various challenges arise when operating standard SRAM circuits at low voltages. These include loss of static noise margins, extreme fluctuations in device currents under process variations and limitations on the number of cells connected to a single bitline. In this paper, we describe the challenges that arise while operating standard SRAM cells at low supply voltages and review several novel bitcells that have been presented in recent years to deal with these challenges.
KW - Near-threshold circuit design
KW - SRAM
KW - Sub-threshold circuit design
KW - Ultra low power digital systems
UR - http://www.scopus.com/inward/record.url?scp=78651255616&partnerID=8YFLogxK
U2 - 10.1109/eeei.2010.5662147
DO - 10.1109/eeei.2010.5662147
M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???
AN - SCOPUS:78651255616
SN - 9781424486809
T3 - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
SP - 608
EP - 612
BT - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
T2 - 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010
Y2 - 17 November 2010 through 20 November 2010
ER -