Study and Analysis of Advanced 3D Multi-Gate Junctionless Transistors

Raj Kumar, Shashi Bala, Arvind Kumar

Research output: Contribution to journalReview articlepeer-review

6 Scopus citations


As the IC technology is evolving very rapidly, the feature size of the device has been migrating to sub-nanometre regime for achieving the high packing density. To continue with further scaling of ICs, some novel devices such as multiple-gate silicon-on-insulator (SOI) devices, Gate-All-Around (GAA) nanowire and Nanotube MOSFETs have been proposed by researchers in recent years. The short channel transistor below 10 nm needs to have ultra-sharp junctions at source and drain ends with the channel region. The creation of such a sharp junction is quite challenging process from fabrication point of view. Therefore, junctionless transistors (JLT) were proposed to eradicate junction’s related issues, exhibit full CMOS functionality. The multigate junctionless transistors have been proposed, designed and fabricated. This paper illustrated basic working mechanism and behaviour of the various single and multi-gate junctionless MOSFETs. Junctionless nanowires transistor with single circular gate and gate material engineered techniques has also been explained. From simulation results, it has been observed that junctionless Nanotube GAA MOSFET has shown superior electrical behaviour over the Nanowire GAA MOSFET. Junctionless GaAs-Nanotube MOSFET has shown tremendous response over Junctionless Si-Nanotube MOSFET in terms of leakage and ON current. Junctionless GaAs-Nanotube MOSFET may be observed as alternate candidate for future CMOS applications.

Original languageEnglish
Pages (from-to)1053-1067
Number of pages15
Issue number3
StatePublished - Feb 2022
Externally publishedYes

Bibliographical note

Funding Information:
Raj Kumar acknowledges the RGNF (UGC) for the financial assistance and UIET (ECE), Panjab University for providing Lab facility.

Publisher Copyright:
© 2020, Springer Nature B.V.


  • High-k
  • Junctionless
  • Nanotube
  • Nanowire
  • SCE
  • Subthreshold


Dive into the research topics of 'Study and Analysis of Advanced 3D Multi-Gate Junctionless Transistors'. Together they form a unique fingerprint.

Cite this