State space modeling for sub-threshold SRAM stability analysis

Keyphrases

• 40nm CMOS 50%
• Analytical Method 50%
• Bitcell 50%
• Bitcell Design 50%
• Brute Force Approach 50%
• CAD Tools 50%
• CMOS Technology 50%
• Dynamic Noise Margin 50%
• Dynamic Stability Analysis 50%
• Fast Evaluation 50%
• Gross Margin Analysis 50%
• Low-voltage Operation 50%
• Order of Magnitude 50%
• Phase Portrait 50%
• SRAM Cell 100%
• SRAM Reliability 100%
• Stability Analysis 100%
• State Phase 50%
• State Space Portrait 50%
• State-space Model 100%
• Static Noise Margin 50%
• Subthreshold 50%
• Subthreshold Regime 50%
• Subthreshold SRAM 100%
• Technology Scaling 50%

Engineering

• Computer Aided Design 33%
• Dynamic Stability 33%
• Metrics 66%
• Noise Margin 66%
• Phase Portrait 33%
• Stability Analysis 100%
• State Space Modeling 100%