Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Robert Giterman, Adam Teman, Pascal Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish

Research output: Contribution to journalArticlepeer-review

32 Scopus citations


Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated with a 2-kb memory macro that was designed and fabricated in a mature 0.18-μm CMOS process, targeted at low-power, energy-efficient applications. The test array is powered with a single supply of 900 mV, showing a 0.8-ms worst case retention time, a 1.3-ns write-access time, and a 2.4-pW/bit retention power. The proposed topology provides a bitcell area reduction of 43%, as compared with a redrawn 6-transistor SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

Original languageEnglish
Article number7031447
Pages (from-to)358-362
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number1
StatePublished - Jan 2016

Bibliographical note

Publisher Copyright:
© 2015 IEEE.


  • Access speed
  • data retention time
  • embedded DRAM
  • gain cell
  • low power operation


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