Simulation Analysis of DMTJ-Based STT-MRAM Operating at Cryogenic Temperatures

Esteban Garzon, Raffaele De Rose, Felice Crupi, Mario Carpentieri, Adam Teman, Marco Lanuzza

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16 Scopus citations


This article investigates spin-transfer torque magnetic random access memories (STT-MRAMs) based on double-barrier magnetic tunnel junction (DMTJ) with two reference layers when operating at cryogenic temperatures. Our study is based on architecture-level estimations relying on preliminary bitcell-level electrical simulations, which have been carried out by exploiting a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm cryogenic-aware CMOS technology. Compared to conventional six-transistor static random access memory (6T-SRAM), DMTJ-based STT-MRAM proves to be faster under read access and less energy-hungry under both read/write accesses for medium to large memory sizes. Quantitatively, compared to its 6T-SRAM counterpart, a 2 MB DMTJ-based STT-MRAM operating at 77 K improves read access time by 28% and energy consumption by 52% and 38% for read and write operations, respectively. This is achieved while providing considerably lower leakage power (-98%) and a smaller on-chip area (by about $3\times $ ), at the only cost of worsened write access time.

Original languageEnglish
Article number9406050
JournalIEEE Transactions on Magnetics
Issue number7
StatePublished - Jul 2021

Bibliographical note

Publisher Copyright:
© 1965-2012 IEEE.


  • 77 K
  • compact model
  • cryogenic computing
  • double-barrier magnetic tunnel junction (DMTJ)
  • spin-transfer torque magnetic random access memory (STT-MRAM)


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