Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from -40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.

Original languageEnglish
Article number9153856
Pages (from-to)1639-1643
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number9
StatePublished - Sep 2020

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.


  • Dual mode logic (DML)
  • PVT variation tolerance
  • adaptive circuits


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