SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate

Yehuda Kra; Yoav Weitzman; Adam Teman

doi:10.1109/dcis55711.2022.9970146

SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate

Yehuda Kra, Yoav Weitzman, Adam Teman

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a transistor sizing algorithm and utility for soft-error (SER) protection circuits. The algorithm applies a gradient-descent convergence scheme for rapidly calculating an optimized sizing configuration per specific protection circuit instance. The utility efficiently interacts with commercial SPICE circuit-level tools for highest accuracy. The analysis and optimization flow is distributed over parallel compute resources to provide a scalable and feasible solution for large designs. The solution is demonstrated on two configurations of the Muller C-element circuit, a widely used component for SER protection across designs. By sizing the test circuits with the proposed utility, a SER protection improvement of as much as two orders-of-magnitude is achieved over a baseline design within minutes of compute runtime.

Original language	English
Title of host publication	DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665459501
DOIs	https://doi.org/10.1109/dcis55711.2022.9970146
State	Published - 2022
Event	37th Conference on Design of Circuits and Integrated Systems, DCIS 2022 - Pamplona, Spain Duration: 16 Nov 2022 → 18 Nov 2022

Publication series

Name	DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems

Conference

Conference	37th Conference on Design of Circuits and Integrated Systems, DCIS 2022
Country/Territory	Spain
City	Pamplona
Period	16/11/22 → 18/11/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Funding

ACKNOWLEDGMENTS This work was partially supported by the Israel Innovation Authority (IIA) under the Kamin program and by the Israel Science Foundation (ISF) grant number 996/18. The authors would like to thank Matan Ben-Moshe for his work on this project.

Funders	Funder number
IIA
Israel Innovation Authority
Israel Science Foundation	996/18

Access to Document

10.1109/dcis55711.2022.9970146

Cite this

Kra, Y., Weitzman, Y., & Teman, A. (2022). SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. In DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems (DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/dcis55711.2022.9970146

Kra, Yehuda ; Weitzman, Yoav ; Teman, Adam. / SerOpt : Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems. Institute of Electrical and Electronics Engineers Inc., 2022. (DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems).

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abstract = "This paper presents a transistor sizing algorithm and utility for soft-error (SER) protection circuits. The algorithm applies a gradient-descent convergence scheme for rapidly calculating an optimized sizing configuration per specific protection circuit instance. The utility efficiently interacts with commercial SPICE circuit-level tools for highest accuracy. The analysis and optimization flow is distributed over parallel compute resources to provide a scalable and feasible solution for large designs. The solution is demonstrated on two configurations of the Muller C-element circuit, a widely used component for SER protection across designs. By sizing the test circuits with the proposed utility, a SER protection improvement of as much as two orders-of-magnitude is achieved over a baseline design within minutes of compute runtime.",

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Kra, Y, Weitzman, Y & Teman, A 2022, SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. in DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems. DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, Institute of Electrical and Electronics Engineers Inc., 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022, Pamplona, Spain, 16/11/22. https://doi.org/10.1109/dcis55711.2022.9970146

SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. / Kra, Yehuda; Weitzman, Yoav; Teman, Adam.
DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems. Institute of Electrical and Electronics Engineers Inc., 2022. (DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a transistor sizing algorithm and utility for soft-error (SER) protection circuits. The algorithm applies a gradient-descent convergence scheme for rapidly calculating an optimized sizing configuration per specific protection circuit instance. The utility efficiently interacts with commercial SPICE circuit-level tools for highest accuracy. The analysis and optimization flow is distributed over parallel compute resources to provide a scalable and feasible solution for large designs. The solution is demonstrated on two configurations of the Muller C-element circuit, a widely used component for SER protection across designs. By sizing the test circuits with the proposed utility, a SER protection improvement of as much as two orders-of-magnitude is achieved over a baseline design within minutes of compute runtime.

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Kra Y, Weitzman Y, Teman A. SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. In DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems. Institute of Electrical and Electronics Engineers Inc. 2022. (DCIS 2022 - Proceedings of the 37th Conference on Design of Circuits and Integrated Systems). doi: 10.1109/dcis55711.2022.9970146

SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate

Abstract

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