Abstract
This paper presents methods for designing totally self-checking Mealy type synchronous sequential circuits (SSCs). We use implementations of the output and next state functions that are monotonic in state variables. The monotony enables the SSC to react to permanent faults differently than it does to transient faults. If the fault is permanent, the SSC will produce a non-code output, which will be detected as error by the checker after a number of clock cycles. In the case of a transient fault, the SSC is able to survive and to return to normal operation after a number of clock cycles. A novel universal architecture of self-checking SSCs enabling to overcome the above contradiction is proposed. This architecture can be adopted both for reduction of the fault latency of a permanent fault and for increasing the SSC survivability with respect to a transient fault. A method for SSC synthesis for the proposed architecture is presented. This method is oriented to FPGA implementation.
Original language | English |
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Title of host publication | Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 44-48 |
Number of pages | 5 |
ISBN (Electronic) | 0769516416, 9780769516417 |
DOIs | |
State | Published - 2002 |
Externally published | Yes |
Event | 8th IEEE International On-Line Testing Workshop, IOLTW 2002 - Isle of Bendor, France Duration: 8 Jul 2002 → 10 Jul 2002 |
Publication series
Name | Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002 |
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Conference
Conference | 8th IEEE International On-Line Testing Workshop, IOLTW 2002 |
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Country/Territory | France |
City | Isle of Bendor |
Period | 8/07/02 → 10/07/02 |
Bibliographical note
Publisher Copyright:© 2002 IEEE.
Funding
This research was supported by BSF under grant No. 9800154
Funders | Funder number |
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United States-Israel Binational Science Foundation | 9800154 |