Self-checking of FPGA-based control units

Ilya Levin, Vladimir Sinelnikov

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations


The paper introduces a new technique for on-line checking of FPGA based Control Units (CUs). This technique is based on the architecture comprising two portions: a self-checking CU and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an Evolution block and an Execution block. Comparison of code vectors being transferred between the blocks of the portions enables providing a totally self-checking property. The self-checking CU is implemented in a form of one-rail network of interconnected pre-designed LUT-based configurable logical blocks. The self-checking checker is a Sum-Of-Minterms based checker. The proposed technique: a) does not require any encoding of output words; b) uses one-rail design, thereby drastically decreasing the required overhead.

Original languageEnglish
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
Number of pages4
ISBN (Print)0769501044
StatePublished - 1999
Externally publishedYes
EventProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Duration: 4 Mar 19996 Mar 1999

Publication series

NameProceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)1066-1395


ConferenceProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
CityAnn Arbor, MI, USA


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