Security Aware Pseudo-Asynchronous Circuit Design Style

A. Fish, I. Levi, O. Keren

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


The increasing demand for electronic systems with increasing bandwidth and decreasing size puts more high-speed circuitry and high bandwidth channels in ever-closer proximity. System-on-a-chip (SoC) integration places complex high speed digital circuitry, analog and RF blocks very closely together. Note that most EDA tools are geared for a specific design type (digital, analog, RF, etc.) However, there are many challenges caused by the interaction across various blocks. These challenges are not limited by the boundaries or types of the various design components, or by the types of analyses that designers are used to regularly run on less complex homogenous designs. Most notable among these interdisciplinary mixed signal SOC challenges include: • Verification of behavioral and electrical correctness • Security verification • Electromagnetic Crosstalk interference analysis and signoff
Original languageAmerican English
Title of host publication2nd IEEE International Verification and Security Workshop
StatePublished - 2017

Bibliographical note

Place of conference:Greece


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