Secured Dual-Rail-Precharge Mux-Based (DPMUX) Symmetric-Logic for Low Voltage Applications

A. Fish, O. Keren, D. Zooker, I. Levi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Hardware implementations of cryptographic algorithms may leak information through numerous side channels, which can be used to reveal the secret cryptographic keys, and therefore compromise the security of the algorithm. Power Analysis Attacks (PAAs) [1] exploit the information leakage from the device's power consumption (typically measured on the supply and/or ground pins). Digital circuits consume dynamic switching energy when data propagate through the logic in each new calculation (e.g. new clock cycle). The average power dissipation of a design can be expressed by: P tot (t) = α · (P d (t) + P pvt (t)) (1) where α is the activity factor (the probability that the gate will switch) and depends on the probability distribution of the inputs to the combinatorial logic. This induces a linear relationship between the power and the processed data [2]. P d is the deterministic power dissipated by the switching of the gate, including any parasitic and intrinsic capacitances, and hence can be evaluated prior to manufacturing. P pvt is the change in expected power consumption due to nondeterministic parameters such as process variations, mismatch, temperature, etc. In this manuscript, we describe the design of logic gates that induce data-independent (constant) α and P d .
Original languageAmerican English
Title of host publication2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
StatePublished - 2017

Bibliographical note

Place of conference:USA


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