TY - GEN
T1 - Secured Dual Mode Logic (DML) as a countermeasure against Differential Power Analysis
AU - Avital, Moshe
AU - Fish, Alexander
PY - 2014
Y1 - 2014
N2 - Security of the digital systems is under the threat from so called side channel attacks. In particular, Differential Power Analysis (DPA) is a powerful technique, as it does not require any assumption regarding the chip implementation of the device. In this paper, we introduce a novel countermeasure strategy to deal with DPA attacks. This approach is based on randomization methodology of the Dual Mode Logic (DML) family. This logic family basically comprises two modes of operation: static and dynamic modes, each having a different power profile. We design the desired cryptographic module using DML gates while switching randomly between operation modes of these gates. This results in power profile which is much more difficult to estimate, and therefore makes the DPA attack less effective. Simulation results, conducted in a standard 40nm technology, prove the efficiency of the proposed methodology.
AB - Security of the digital systems is under the threat from so called side channel attacks. In particular, Differential Power Analysis (DPA) is a powerful technique, as it does not require any assumption regarding the chip implementation of the device. In this paper, we introduce a novel countermeasure strategy to deal with DPA attacks. This approach is based on randomization methodology of the Dual Mode Logic (DML) family. This logic family basically comprises two modes of operation: static and dynamic modes, each having a different power profile. We design the desired cryptographic module using DML gates while switching randomly between operation modes of these gates. This results in power profile which is much more difficult to estimate, and therefore makes the DPA attack less effective. Simulation results, conducted in a standard 40nm technology, prove the efficiency of the proposed methodology.
UR - http://www.scopus.com/inward/record.url?scp=84907397862&partnerID=8YFLogxK
U2 - 10.1109/iscas.2014.6865259
DO - 10.1109/iscas.2014.6865259
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AN - SCOPUS:84907397862
SN - 9781479934324
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 810
EP - 813
BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Y2 - 1 June 2014 through 5 June 2014
ER -