Abstract
The dominant state-of-the-art approach for solving bit-vector formulas in Satisfiability Modulo Theories (SMT) is bit-blasting, an eager reduction to propositional logic. Bit-blasting is surprisingly efficient in practice but does not generally scale well with increasing bit-widths, especially when bit-vector arithmetic is present. In this paper, we present a novel CEGAR-style abstraction-refinement procedure for the theory of fixed-size bit-vectors that significantly improves the scalability of bit-blasting. We provide lemma schemes for various arithmetic bit-vector operators and an abduction-based framework for synthesizing refinement lemmas. We extended the state-of-the-art SMT solver Bitwuzla with our abstraction-refinement approach and show that it significantly improves solver performance on a variety of benchmark sets, including industrial benchmarks that arise from smart contract verification.
Original language | English |
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Title of host publication | Computer Aided Verification - 36th International Conference, CAV 2024, Proceedings |
Editors | Arie Gurfinkel, Vijay Ganesh |
Publisher | Springer Science and Business Media Deutschland GmbH |
Pages | 178-200 |
Number of pages | 23 |
ISBN (Print) | 9783031656262 |
DOIs | |
State | Published - 2024 |
Event | 36th International Conference on Computer Aided Verification, CAV 2024 - Montreal, Canada Duration: 24 Jul 2024 → 27 Jul 2024 |
Publication series
Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
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Volume | 14681 LNCS |
ISSN (Print) | 0302-9743 |
ISSN (Electronic) | 1611-3349 |
Conference
Conference | 36th International Conference on Computer Aided Verification, CAV 2024 |
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Country/Territory | Canada |
City | Montreal |
Period | 24/07/24 → 27/07/24 |
Bibliographical note
Publisher Copyright:© The Author(s) 2024.