Resistive Associative Processor

Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar

Research output: Contribution to journalArticlepeer-review

63 Scopus citations


Associative Processor (AP) combines data storage and data processing, and functions simultaneously as a massively parallel array SIMD processor and memory. Traditionally, AP is based on CMOS technology, similar to other classes of massively parallel SIMD processors. The main component of AP is a Content Addressable Memory (CAM) array. As CMOS feature scaling slows down, CAM experiences scalability problems. In this work, we propose and investigate an AP based on resistive CAM - the Resistive AP (ReAP). We show that resistive memory technology potentially allows scaling the AP from a few millions to a few hundred millions of processing units on a single silicon die. We compare the performance and power consumption of a ReAP to a CMOS AP and a conventional SIMD accelerator (GPU) and show that ReAP, although exhibiting higher power density, allows better scalability and higher performance.

Original languageEnglish
Article number6966736
Pages (from-to)148-151
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number2
StatePublished - 1 Jul 2015
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2015 IEEE.


  • SIMD
  • associative processor
  • in-memory computing
  • memristor
  • resistive RAM


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