Resistive address decoder

Leonid Yavits, Uri Weiser, Ran Ginosar

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

—Hardwired dynamic NAND address decoders are widely used in random access memories to decode parts of the address. Replacing wires by resistive elements allows storing and reprogramming the addresses and matching them to an input address. The resistive address decoder thus becomes a content addressable memory, while the read latency and dynamic energy remain almost identical to those of a hardwired address decoder. One application of the resistive address decoder is a fully associative TLB with read latency and energy consumption similar to those of a one-way associative TLB. Another application is a many-way associative cache with read latency and energy consumption similar to those of a direct mapped one. A third application is elimination of physical addressing and using virtual addresses throughout the entire memory hierarchy by introducing the resistive address decoder into the main memory.

Original languageEnglish
Pages (from-to)141-144
Number of pages4
JournalIEEE Computer Architecture Letters
Volume16
Issue number2
DOIs
StatePublished - 1 Jul 2017
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2017 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

Keywords

  • Address decoder
  • CAM
  • Cache
  • Memristors
  • Physical address
  • RAM
  • Resistive memory
  • TLB
  • Virtual address

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