Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Keyphrases

• Gain Cell 100%
• EDRAM 100%
• Logic Compatible 100%
• Bitline 100%
• Refresh Operation 60%
• Latency 40%
• Static Random Access Memory 40%
• Storage Mechanism 20%
• Energy Conservation 20%
• Energy Overhead 20%
• Embedded Memory 20%
• Memory Controller 20%
• Area Overhead 20%
• High Density 20%
• Integrated Circuits 20%
• Refresh Cycle 20%
• Low Power Consumption 20%
• Read Energy 20%
• Dynamic Storage 20%
• Limited Memory 20%
• Single Clock 20%

Engineering

• Internals 100%
• Bit Line 100%
• Energy Engineering 50%
• Random Access Memory 50%
• Integrated Circuit 25%
• Low Power Consumption 25%
• Area Overhead 25%
• Realization 25%
• Memory Controller 25%
• Clock Cycle 25%

Medicine and Dentistry

• Health Care Cost 100%