Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Pascal Meinerzhagen; Andrea Bonetti; Georgios Karakonstantis; Christoph Roth; Frank Giirkaynak; Andreas Burg

doi:10.1109/ISCAS.2015.7168911

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Pascal Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Burg

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

Original language	English
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1426-1429
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7168911
State	Published - 27 Jul 2015
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 24 May 2015 → 27 May 2015

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	24/05/15 → 27/05/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Access to Document

10.1109/ISCAS.2015.7168911

Cite this

Meinerzhagen, P., Bonetti, A., Karakonstantis, G., Roth, C., Giirkaynak, F., & Burg, A. (2015). Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 1426-1429). Article 7168911 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168911

Meinerzhagen, Pascal ; Bonetti, Andrea ; Karakonstantis, Georgios et al. / Refresh-free dynamic standard-cell based memories : Application to a QC-LDPC decoder. 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1426-1429 (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{131879e4cce14b898d47b66d68116e42,

title = "Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder",

abstract = "The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).",

author = "Pascal Meinerzhagen and Andrea Bonetti and Georgios Karakonstantis and Christoph Roth and Frank Giirkaynak and Andreas Burg",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Symposium on Circuits and Systems, ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",

year = "2015",

month = jul,

day = "27",

doi = "10.1109/ISCAS.2015.7168911",

language = "אנגלית",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1426--1429",

booktitle = "2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015",

address = "ארצות הברית",

}

Meinerzhagen, P, Bonetti, A, Karakonstantis, G, Roth, C, Giirkaynak, F & Burg, A 2015, Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7168911, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 1426-1429, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 24/05/15. https://doi.org/10.1109/ISCAS.2015.7168911

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. / Meinerzhagen, Pascal; Bonetti, Andrea; Karakonstantis, Georgios et al.
2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1426-1429 7168911 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Refresh-free dynamic standard-cell based memories

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015

AU - Meinerzhagen, Pascal

AU - Bonetti, Andrea

AU - Karakonstantis, Georgios

AU - Roth, Christoph

AU - Giirkaynak, Frank

AU - Burg, Andreas

PY - 2015/7/27

Y1 - 2015/7/27

N2 - The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

AB - The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

UR - http://www.scopus.com/inward/record.url?scp=84946223844&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2015.7168911

DO - 10.1109/ISCAS.2015.7168911

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:84946223844

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1426

EP - 1429

BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 24 May 2015 through 27 May 2015

ER -

Meinerzhagen P, Bonetti A, Karakonstantis G, Roth C, Giirkaynak F, Burg A. Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1426-1429. 7168911. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2015.7168911

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Abstract

Publication series

Conference

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this