Refined Analytical em Model of IC-Internal Shielding for Hardware-Security and Intra-Device Simulative Framework

Over the past two decades, the prominence of physical attacks on electronic devices, designed to extract confidential information, has surged. These attacks exploit the inherent physical characteristics of integrated circuits (ICs), leading to information leakage. While several cutting-edge countermeasures have been developed to thwart attempts at obtaining sensitive data, the potential of shielding as a defensive mechanism has not been comprehensively explored within the realm of ICs. Shielding, with its capabilities encompassing the reduction of electromagnetic (EM) radiation leakage, detection of penetration attempts, and the obfuscation of adversaries' measurement efforts, presents an intriguing avenue for safeguarding information. Remarkably, the investigation into the efficacy of shielding in minimizing EM radiation leakage and consequently curtailing information leakage has been somewhat limited in the context of ICs. This limitation extends to various aspects, including the topological configuration of shields, the development of a comprehensive analytical model for leakage assessment, and the simulation capacity prior to the silicon fabrication stage. Previous state-of-the-art (SOTA) reports have primarily concentrated on the prevention of probing or penetration of shielding mechanisms. In our research, we contribute a fully refined analytical model tailored for IC shielding, capable of accurately estimating fields in presence of shields and evaluating security against a spectrum of IC hardware (HW) attacks. Importantly, we introduce a simulation methodology employing CAD tools, IC Process Design Kit (PDK), and Ansys HFSS to evaluate shielding performance within layouts directly imported from a commercial CAD and IC PDKs, following the integration of full-chip tools.