Abstract
The unique properties of spin-transfer torque magnetic tunnel junctions (STT-MTJs) have led to promising designs for logic and memory applications. Additionally, STT-MTJ based circuits have shown attractive potential to design efficient non-volatile logic-in-memory (NV-LIM) architectures, which assure low power and increased speed. This paper proposes a bit-level reconfigurable NV logic circuit based on hybrid CMOS/STT-MTJ design. Indeed, our circuit can adapt on-demand its structure, thus offering intrinsic flexibility to perform basic logic functions (i.e. AND/OR/XOR) by a single circuit architecture. Post-layout simulation results prove that the proposed circuit leads to increase both delay and energy consumption with respect to state-of-the-art non-reconfigurable designs. However, its reconfigurable operation capability is very attractive to reduce area occupation and to increase design flexibility of NV-LIM systems.
Original language | English |
---|---|
Title of host publication | 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781728134277 |
DOIs | |
State | Published - Feb 2020 |
Event | 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 - San Jose, Costa Rica Duration: 25 Feb 2020 → 28 Feb 2020 |
Publication series
Name | 2020 IEEE 11th Latin American Symposium on Circuits and Systems, LASCAS 2020 |
---|
Conference
Conference | 11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020 |
---|---|
Country/Territory | Costa Rica |
City | San Jose |
Period | 25/02/20 → 28/02/20 |
Bibliographical note
Publisher Copyright:© 2020 IEEE.
Keywords
- Magnetic tunnel junction (MTJ)
- logic-in-memory (LIM)
- non-volatile logic gates
- spin-transfer torque (STT)