PSL assertion checkers synthesis with ASM based HLS tool ABELITE

Maksim Jenihhin; Samary Baranov; Jaan Raik; Valentin Tihhomirov

doi:10.1109/LATW.2012.6261251

PSL assertion checkers synthesis with ASM based HLS tool ABELITE

Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Tallinn University of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach utilizes Algorithmic State Machines (ASMs) based High Level Synthesis (HLS) tool ABELITE. It targets creation of functionally and temporally correct checkers that provide comprehensive assertion checking debug information during emulation. The paper contributions include a new methodology for PSL assertions translation to ASM representations and a new approach for the HLS tool ABELITE application for correct by construction assertion generation. Experimental results demonstrate feasibility and effectiveness of the proposed approach.

Original language	English
Title of host publication	LATW 2012 - 13th IEEE Latin American Test Workshop
DOIs	https://doi.org/10.1109/LATW.2012.6261251
State	Published - 2012
Event	13th IEEE Latin American Test Workshop, LATW 2012 - Quito, Ecuador Duration: 10 Apr 2012 → 13 Apr 2012

Publication series

Name	LATW 2012 - 13th IEEE Latin American Test Workshop

Conference

Conference	13th IEEE Latin American Test Workshop, LATW 2012
Country/Territory	Ecuador
City	Quito
Period	10/04/12 → 13/04/12

Keywords

Algorithmic State Machines (ASMs)
High-Level Synthesis (HLS)
Property Specification Language (PSL)
assertion checkers
debug
emulation

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10.1109/LATW.2012.6261251

Cite this

@inproceedings{d8b7ae42659541778653429d33603c3b,

title = "PSL assertion checkers synthesis with ASM based HLS tool ABELITE",

abstract = "This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach utilizes Algorithmic State Machines (ASMs) based High Level Synthesis (HLS) tool ABELITE. It targets creation of functionally and temporally correct checkers that provide comprehensive assertion checking debug information during emulation. The paper contributions include a new methodology for PSL assertions translation to ASM representations and a new approach for the HLS tool ABELITE application for correct by construction assertion generation. Experimental results demonstrate feasibility and effectiveness of the proposed approach.",

keywords = "Algorithmic State Machines (ASMs), High-Level Synthesis (HLS), Property Specification Language (PSL), assertion checkers, debug, emulation",

author = "Maksim Jenihhin and Samary Baranov and Jaan Raik and Valentin Tihhomirov",

year = "2012",

doi = "10.1109/LATW.2012.6261251",

language = "אנגלית",

isbn = "9781467323567",

series = "LATW 2012 - 13th IEEE Latin American Test Workshop",

booktitle = "LATW 2012 - 13th IEEE Latin American Test Workshop",

note = "13th IEEE Latin American Test Workshop, LATW 2012 ; Conference date: 10-04-2012 Through 13-04-2012",

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T1 - PSL assertion checkers synthesis with ASM based HLS tool ABELITE

AU - Jenihhin, Maksim

AU - Baranov, Samary

AU - Raik, Jaan

AU - Tihhomirov, Valentin

PY - 2012

Y1 - 2012

N2 - This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach utilizes Algorithmic State Machines (ASMs) based High Level Synthesis (HLS) tool ABELITE. It targets creation of functionally and temporally correct checkers that provide comprehensive assertion checking debug information during emulation. The paper contributions include a new methodology for PSL assertions translation to ASM representations and a new approach for the HLS tool ABELITE application for correct by construction assertion generation. Experimental results demonstrate feasibility and effectiveness of the proposed approach.

AB - This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach utilizes Algorithmic State Machines (ASMs) based High Level Synthesis (HLS) tool ABELITE. It targets creation of functionally and temporally correct checkers that provide comprehensive assertion checking debug information during emulation. The paper contributions include a new methodology for PSL assertions translation to ASM representations and a new approach for the HLS tool ABELITE application for correct by construction assertion generation. Experimental results demonstrate feasibility and effectiveness of the proposed approach.

KW - Algorithmic State Machines (ASMs)

KW - High-Level Synthesis (HLS)

KW - Property Specification Language (PSL)

KW - assertion checkers

KW - debug

KW - emulation

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AN - SCOPUS:84866927715

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T3 - LATW 2012 - 13th IEEE Latin American Test Workshop

BT - LATW 2012 - 13th IEEE Latin American Test Workshop

T2 - 13th IEEE Latin American Test Workshop, LATW 2012

Y2 - 10 April 2012 through 13 April 2012

ER -

PSL assertion checkers synthesis with ASM based HLS tool ABELITE

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