Abstract
A method for the programming and evaluation of parallel signal-processor architectures based on a data-flow representation of signal-processing algorithms is described. The constant data flow, which is a special property of most signal-processing algorithms, allows the scheduling and resource allocation to be done at compile time, rather than at run time as in usual data-flow systems. It is therefore possible to describe arbitrary hardware configurations; a result that is closer to a realizable hardware solution is guaranteed. Therefore hardware requirements can be kept low. 7 refs.
| Original language | English |
|---|---|
| Pages (from-to) | 378-381 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| State | Published - 1987 |
| Externally published | Yes |