Post-Silicon Analysis of Shielded Interconnect Delays for Useful Skew Clock Design

Binyamin Frankel, Eyal Sarfati, Shmuel Wimer, Yitzhak Birk

Research output: Contribution to journalArticlepeer-review


Analyses and simulations have shown that interconnect shielding can replace a large fraction of the delay buffers used to achieve timing goals through a useful skew clock design methodology. Immunity from process, operation, and environmental variations in nanoscale CMOS technology clock designs are essential, thus making predictable delays and useful skews highly important. We examine interconnect shielding intradie within-die (WID) and interdie die-to-die (D2D) variations under a wide variety of (P,V,T) corners, and show their applicability and ability to achieve clock design timing goals. The analysis is based on post-silicon measurements of a novel shielded interconnect ring oscillator in a 16-nm test chip supported by a rigorous provable estimation methodology.

Original languageEnglish
Article number8844248
Pages (from-to)4875-4882
Number of pages8
JournalIEEE Transactions on Electron Devices
Issue number11
StatePublished - Nov 2019

Bibliographical note

Funding Information:
Manuscript received July 8, 2019; revised August 14, 2019; accepted August 27, 2019. Date of publication September 18, 2019; date of current version October 29, 2019. This work was supported by the Israel Chief Scientist through the HiPer Consortium of the MAGNET Program. The review of this article was arranged by Editor M. S. Bakir. (Corresponding author: Shmuel Wimer.) B. Frankel and S. Wimer are with the Engineering Faculty, Bar-Ilan University, Ramat Gan 52900, Israel (e-mail:;

Publisher Copyright:
© 1963-2012 IEEE.


  • Clock trees
  • delay tuning
  • interconnections
  • process variations
  • ring oscillator (RO)
  • useful skew
  • wire shielding


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