Post-Silicon Analysis of Shielded Interconnect Delays for Useful Skew Clock Design

Binyamin Frankel; Eyal Sarfati; Shmuel Wimer; Yitzhak Birk

doi:10.1109/ted.2019.2938621

Post-Silicon Analysis of Shielded Interconnect Delays for Useful Skew Clock Design

Binyamin Frankel, Eyal Sarfati, Shmuel Wimer, Yitzhak Birk

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Technion-Israel Institute of Technology

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

Analyses and simulations have shown that interconnect shielding can replace a large fraction of the delay buffers used to achieve timing goals through a useful skew clock design methodology. Immunity from process, operation, and environmental variations in nanoscale CMOS technology clock designs are essential, thus making predictable delays and useful skews highly important. We examine interconnect shielding intradie within-die (WID) and interdie die-to-die (D2D) variations under a wide variety of (P,V,T) corners, and show their applicability and ability to achieve clock design timing goals. The analysis is based on post-silicon measurements of a novel shielded interconnect ring oscillator in a 16-nm test chip supported by a rigorous provable estimation methodology.

Original language	English
Article number	8844248
Pages (from-to)	4875-4882
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	11
DOIs	https://doi.org/10.1109/ted.2019.2938621
State	Published - Nov 2019

Bibliographical note

Publisher Copyright:
© 1963-2012 IEEE.

Funding

Manuscript received July 8, 2019; revised August 14, 2019; accepted August 27, 2019. Date of publication September 18, 2019; date of current version October 29, 2019. This work was supported by the Israel Chief Scientist through the HiPer Consortium of the MAGNET Program. The review of this article was arranged by Editor M. S. Bakir. (Corresponding author: Shmuel Wimer.) B. Frankel and S. Wimer are with the Engineering Faculty, Bar-Ilan University, Ramat Gan 52900, Israel (e-mail: [email protected]; [email protected]).

Funders	Funder number
Israel Chief Scientist

Keywords

Clock trees
delay tuning
interconnections
process variations
ring oscillator (RO)
useful skew
wire shielding

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10.1109/ted.2019.2938621

Cite this

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Post-Silicon Analysis of Shielded Interconnect Delays for Useful Skew Clock Design

Abstract

Bibliographical note

Funding

Keywords

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