PIPELINE MULTIPROCESSOR ARCHITECTURE FOR HIGH SPEED CELL IMAGE ANALYSIS.

Kenneth R. Castleman; Kenneth H. Price; Raymond Eskenazi; Musa M. Ovadya; Mois A. Navon

PIPELINE MULTIPROCESSOR ARCHITECTURE FOR HIGH SPEED CELL IMAGE ANALYSIS.

Kenneth R. Castleman, Kenneth H. Price, Raymond Eskenazi, Musa M. Ovadya, Mois A. Navon

Department of Jewish Philosophy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Original language	English
Title of host publication	IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma
Publisher	IEEE
Pages	52-54
Number of pages	3
ISBN (Print)	0818604980
State	Published - 1983

Publication series

Name	IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma

Cite this

Castleman, K. R., Price, K. H., Eskenazi, R., Ovadya, M. M., & Navon, M. A. (1983). PIPELINE MULTIPROCESSOR ARCHITECTURE FOR HIGH SPEED CELL IMAGE ANALYSIS. In IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma (pp. 52-54). (IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma). IEEE.

@inproceedings{5a8fd40e5ba244d88783469768634797,

title = "PIPELINE MULTIPROCESSOR ARCHITECTURE FOR HIGH SPEED CELL IMAGE ANALYSIS.",

author = "Castleman, {Kenneth R.} and Price, {Kenneth H.} and Raymond Eskenazi and Ovadya, {Musa M.} and Navon, {Mois A.}",

year = "1983",

language = "אנגלית",

isbn = "0818604980",

series = "IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma",

publisher = "IEEE",

pages = "52--54",

booktitle = "IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma",

}

PIPELINE MULTIPROCESSOR ARCHITECTURE FOR HIGH SPEED CELL IMAGE ANALYSIS. / Castleman, Kenneth R.; Price, Kenneth H.; Eskenazi, Raymond et al.
IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma. IEEE, 1983. p. 52-54 (IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - PIPELINE MULTIPROCESSOR ARCHITECTURE FOR HIGH SPEED CELL IMAGE ANALYSIS.

AU - Castleman, Kenneth R.

AU - Price, Kenneth H.

AU - Eskenazi, Raymond

AU - Ovadya, Musa M.

AU - Navon, Mois A.

PY - 1983

Y1 - 1983

UR - http://www.scopus.com/inward/record.url?scp=0020907011&partnerID=8YFLogxK

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:0020907011

SN - 0818604980

T3 - IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma

SP - 52

EP - 54

BT - IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Ma

PB - IEEE

ER -

PIPELINE MULTIPROCESSOR ARCHITECTURE FOR HIGH SPEED CELL IMAGE ANALYSIS.

Publication series

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Cite this