Photonic XOR with inherent loss compensation mechanism for memory cell implementation in a standard nanoscale very large-scale integrated fabrication process

A multilayer photonic XOR gate is presented. The XOR is implemented by the interconnect layers of a microelectronic chip and is suitable for fabrication in a standard VLSI fabrication process. The proposed device features an inherent insertion loss compensation mechanism by utilization of nanometric holes, making it possible to implement an optic memory cell without the need of additional complex compensation devices. The structure of such a memory cell, implemented by utilization of two proposed XOR gates, configured to perform the NOT function, is shown. The unique structure of the proposed device allows us to significantly reduce sensitivity to process variations and therefore makes it possible to utilize the memory cell in state-of-the-art nanoscale processes. The proposed memory can be integrated with conventional electronics on the same VLSI chip.