Abstract
The power consumed when writing to Resistive Random Access Memory (RRAM) is significantly greater than that consumed by many charge-based memories such as SRAM, DRAM and NAND-Flash memories. As a result, when used in applications where instantaneous power consumption is constrained, the number of bits that can be set or reset must not exceed a certain threshold. In this paper, we present a power-efficient, single error correcting (PESEC) code for memory macros, which, when combined with bus encoding, ensures low-power operation and reliable data storage. This systematic, multiple-representation based single-error correcting code provides a relatively high rate, with a marginal increase in implementation cost relative to that of a standard Hamming code, and it can be used with any bus encoder.
| Original language | English |
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| Title of host publication | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9783982674100 |
| DOIs | |
| State | Published - 2025 |
| Event | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Lyon, France Duration: 31 Mar 2025 → 2 Apr 2025 |
Publication series
| Name | Proceedings -Design, Automation and Test in Europe, DATE |
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| ISSN (Print) | 1530-1591 |
Conference
| Conference | 2025 Design, Automation and Test in Europe Conference, DATE 2025 |
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| Country/Territory | France |
| City | Lyon |
| Period | 31/03/25 → 2/04/25 |
Bibliographical note
Publisher Copyright:© 2025 EDAA.
Keywords
- Bus encoding
- Emerging non-volatile memory
- Power-efficient coding
- Resistive RAM (RRAM)
- Single error correction (SEC)
- Write after Read